1. Field of the Invention
The present invention relates to frequency tuning, and more particularly to a phase-locked loop (PLL) circuit having a voltage-controlled oscillator (VCO) and a delay-locked loop (DLL) circuit having a voltage-controlled delay line (VCDL) and methods of tuning output frequencies of the PLL and the DLL.
2. Description of the Related Art
Phase-locked loop (PLL) circuits are widely used to synchronize clocks that are applied to circuit blocks. PLL circuits are used in various electronic systems including, for example, communication systems, multimedia systems, and in various other applications such as frequency modulation (FM) demodulators, clock recovery circuits, tone decoders, etc.
The PLL circuits commonly include a voltage-controlled oscillator (VCO). The operating characteristics of the VCO can have a significant impact on the performance of both the PLL and the system in which the PLL is employed. In many applications, the frequency range of a clock generated by the PLL may be determined depending on the frequency range of an output signal of the VCO.
FIG. 1 is a graph illustrating frequency characteristics of an output signal of a VCO according to operating conditions in a conventional PLL circuit.
As illustrated in FIG. 1, the output signal of a VCO may have different frequency curves according to operating conditions such as process, voltage, and temperature. In the best conditions, the output signal of a VCO may have a higher frequency than the frequency in typical conditions. In the worst conditions, the output signal of a VCO may have a lower frequency than the frequency in the typical conditions. In FIG. 1, VH denotes an upper limit voltage that the oscillation-control voltage VCON may have, and VL denotes a lower limit voltage that the oscillation-control voltage VCON may have.
In the conventional art, changes in VCO characteristics may be compensated for by a temperature-compensating circuit included in the PLL circuit or by securing an increased design margin. However, the temperature compensating circuit may not compensate for changes in VCO characteristics when a fabrication process is changed, and when the design margin has a limit. Further, the operation speed of the VCO should be decreased in order to cover the minimum operational frequency under the best conditions. On the contrary, the operation speed of a VCO should be increased in order to cover the maximum operational frequency under the worst conditions.
Accordingly, a PLL circuit capable of securing a maximum frequency and a minimum frequency regardless of the changes in operating conditions is required.